USR-ES1 is embedded with Wiznet’s W5500 chip, and uses hardware logic gate circuits to implement the transport layer and network layer of the TCP/IP protocol stack (such as: TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE and other protocols), and integrates Data link layer, physical layer, and 32K bytes of on-chip RAM
Cache for sending and receiving data. Make the host computer main control chip only need to undertake the processing task of TCP/IP application layer control information. This greatly saves the workload of the host computer for data replication, protocol processing, and interrupt processing, and improves system utilization and reliability.
During operation, users can use W5500 as a peripheral RAM of MCU, which is very simple. The external interface of W5500 is a general 80MHz high-speed SPI, which can be selected for different platforms to expand high-speed Ethernet solutions. Auto-negotiation LED status shows that the SPI interface is fast and stable.
The size and pins are compatible with Wiznet's official module WIZ820io
Features:
- 80MHz high-speed SPI interface
- Built-in hardware TCPIP protocol stack, users hardly need to master complex network protocol knowledge
- Support up to 8 Socket connections
- Support TCP, UDP, ICMP, IPv4, ARP, IGMP.PPPoE protocol
- Integrated data link layer and physical layer
- Support wake up after power failure
- Support high-speed serial peripheral interface 0 (SPI mode 0~3)
- Internal 32K bytes transmit and receive buffer
- Embedded 10BaseT/1 00BaseTX Ethernet physical layer (PHY)
- Support auto negotiation (10/100-Based full double earth/half double earth)
- Does not support IP fragmentation
- 3.3V working voltage, 1/0 signal port 5V withstand voltage
- LED status display (full duplex/half duplex, network connection, network speed, activity status
- Ultra-small pin-type package, convenient for embedded applications
- Provide C application routines
Parameters:
- Power supply mode: 3.3V external power supply, current should be greater than 200mA
- Control interface form: 3.3V TTL level, _SPI interface, 2*single row pin
- PCB size (MM): 23* 25 mm
- Mechanical size (length * width * height): 28.5* 23* 24 mm
Pin description:
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GND: ground, power negative
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VIN3.3: 3.3V power supply positive
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PWDN: Pin is used for power down mode
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High level: power-down mode enabled
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Low level: Normal mode enabled
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nREST: This pin is active low, used to reset and re-initialize W5500
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MISO: SPI master input and slave output
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MOSI: SPI master output and slave input
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SCLK: SPI clock pin
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nSS: SPI chip select pin, active low
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nINT: interrupt pin, active low
Precautions:
This module is not a SPI-to-Ethernet transparent transmission module, it needs to be used by an external microcontroller, and the user needs to understand the use of the W5500 chip, and provide STM32 example codes.