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SN7476 - Dual J-K Flip-Flop, Preset & Clear

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IC 7476 Dual J-K Flip-Flop, Preset & Clear

The 74LS76 IC is essentially synonymous with JK flip-flops, primarily employed for bit storage but also demonstrating utility in various other applications. Several key attributes contribute to the widespread popularity of JK flip-flops, including:

  • The clock input feature.

  • The presence of preset input pins.

Notably, JK flip-flops exhibit state transitions upon the application of a clock pulse signal, which can manifest as either a positive or negative edge. Furthermore, the 74LS76 possesses the capability to filter out invalid output conditions.

7476 IC Pin Diagram

The following is the pin description of 74LS76:

Pin No. Pin Name Description
5 Vcc Powers the IC typically with 5V
13 Ground Connected to the ground of the system
JK Flip Flop – 1 / JK Flip Flop - 2
1,6 Clock-1/ Clock-2 These pins must be provided with clock pulse for the flip flop
2,7 Preset-1 / Preset-2 Preset input pin drives Flip Flop to a set state
16, 12 1K/ 2K Input pin of the Flip Flop
4,9 1J / 2J Another Input pin of the Flip Flop
14, 10 1Q(bar) / 2Q (bar) Inverted output pin of Flip Flop
15,11 1Q / 2Q Output Pin of the Flip Flop
3,8 1 CLR (bar)/ 2 CLR (bar) Clear input pin drives Flip Flop to a reset state


74ls76 Pin Details:

  • Pin 1(1 CLK): Clock input for the first JK flip-flop. A HIGH to LOW pulse influences this flip-flop.

  • Pin 2(1 PRE'): Preset input for the first flip-flop, setting 1Q to HIGH. Active LOW.

  • Pin 3(1 CLR'): Clear input for the first flip-flop, resetting its output. Active LOW.

  • Pin 4(Input 1, J): First input for the first flip-flop, receiving data (HIGH or LOW).

  • Pin 5(Vcc): Power supply pin, providing operational power to the IC.

  • Pin 6(2 CLK): Clock input for the second JK flip-flop. A HIGH to LOW pulse affects the IC.

  • Pin 7(2 PRE'): Preset input for the second flip-flop, setting 2Q to HIGH. Active LOW.

  • Pin 8(2 CLR'): Clear input for the second flip-flop, resetting its output. Active LOW.

  • Pin 9(Input 2, J): First input for the second flip-flop, receiving data (HIGH or LOW).

  • Pin 10(2Q'): Second output for the second flip-flop, providing the inverted output of Pin 11.

  • Pin 11(OUTPUT 2Q): First output for the second flip-flop, offering its output bit.

  • Pin 12(Input 2K): Second input for the second flip-flop, receiving the second data bit (HIGH or LOW).

  • Pin 13(GND): Ground pin, creating a common ground with the power supply and other devices if required.

  • Pin 14(1Q'): Second output for the first flip-flop, supplying the inverted output of Pin 15.

  • Pin 15(OUTPUT 1Q): First output for the first flip-flop, providing its output bit.

  • Pin 16(Input 1K): Second input for the first flip-flop, receiving the second data bit (HIGH or LO